Yewcy 
yew@movsw.0x0.st
“The trace monoid or free partially commutative monoid is a monoid of traces.”
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Yewcy
yew@movsw.0x0.st
@snacks i have no idea if there’s still desktop cpus with non-trace instruction caches
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The Zen 5 breaks this long-standing bottleneck for the first time with a fetch rate of 32 bytes per clock and a decoding rate of 6 instructions per clock. This fetch and decode rate applies to each side of a 2-way branch when the two branches are decoded simultaneously.
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bartholin (surviving global warming arc)
bartholin@fops.cloud
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mia (developer mode)
mia@shrimptest.0x0.st@snacks @yew zen has clustered decoders (that’s something AMD did with steamroller as well) and zen 5 has two fetch paths for them as well. as long as everything fits into the instruction cache, for 8-byte instructions, excavator actually gets higher throughput than zen 5 and also benefits from SMT, but not as much as zen 5 where throughput doubles with 2 threads.
4-wide instruction decoder too slow? frontend working too hard? literally just add a second cluster lol
having two decode clusters also means zen 5 doesn’t rely quite as heavily on its op cache as zen 4 did, at least for SMT workloads, but switching between instruction cache and op cache mode still hurts performance a lot. usually that’s not a problem because the op cache is massive (6k entries iirc). there are cases where the op cache nearly doubles execution throughput
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